Semiconductor can be increased, which in turn increases

Semiconductor device industry has marched at the pace of Moore’s Law. The number of transistors doubles approximately every two years as a result of continuous scaling of transistors, which has been the distinct feature of the semiconductor manufacturing industry. Each newer generation technology produces more functionality, denser & faster transistors compared to previous generation technology 1.

The size of the transistor is decreasing continuously with the decrease in the thickness of the silicon dioxide gate dielectric to increase the gate capacitance and the drive current, which ultimately provides better device performance 14.  The ultra-scaled CMOS devices are facing challenges due to shrinking geometrics, less supply power, and higher frequencies demands, thereby causing short channel effect which increases the leakage currents in the device constantly. The enhancement in the scaling technology has increased the need of low power circuits 14. In Nano devices, CMOS based circuits are not used due to the problems like Short Channel Effect (SCE), high leakage thereby increasing static power 14. New technologies are needed for handling the various effects of CMOS scaling. The planar CMOS shows significant SCE and hence migration to new device structures with negligible SCE for the same channel length is getting significant attention.



FinFET have significantly captured the attention of the industry over past decade because of the degrading SCE of planar CMOS behaviour. In the planar MOSFET channel is horizontal whereas in FinFET channel is vertical known as Fin. Multiple fins and smaller fin heights leads to more flexibility and width of the channel can be increased, which in turn increases silicon area.


II. Evolution of IC Process technology

A. Bipolar Technology

     The first transistor was developed by John Bardeen, Walter Brattain and William Shockley at Bell laboratories in 1947 which enabled the rapid growth of the semiconductor technology industry. The first integrated circuits (IC) of seventies available in market has a few hundred transistors which were manufactured in bipolar technology 29. Bipolar transistors can be either of NPN or PNP structure. In these bipolar transistors, small current into very thin base region controls the large current between emitter and collector. Base currents limit significantly affects the integration density of these devices 29. Bipolar technology delivered high current drive, high switching speed, smaller delay, high performance, but high power consumption makes very large integration difficult.


B. MOSFET Technology

The Metal-Oxide-Semiconductor Field Effect Transistor commonly known as MOSFET was introduced with very attractive feature of low power consumption, low operating voltage, higher speed etc., which made it useful in electronic design 20. Two types of MOSFET structure namely P-MOSFET and N-MOSFET are used for designing integrated circuits. Unfortunately, both consumes high static power. Frank Wan lass introduced a new logic design known as CMOS using complementary PMOS and NMOS. The main advantage of CMOS technology includes high noise immunity and very low static power consumption. Since CMOS consumes very low power, it allows much higher level of integration because of which innovative CMOS device with excellent features were evident past several decades. The trends of CMOS integrated circuits downsizing are as given below 20.

(2D technology from 1970) 10µm-> 8 µm-> 6 µm -> 4 µm -> 3 µm -> 2 µm -> 1.2 µm -> 0. µm 8-> 0.5 µm -> 0.35 µm -> 0.25 µm -> 180nm->130nm-> 90nm-> 65nm-> 45nm-> 32nm-> 28nm->

(3D technology) -> 22nm (2011)-> 15nm (2013)-> 10nm (2015)-> 7nm (2017) 20.


C. BiCMOS Technology

Bipolar CMOS popularly known as BiCMOS technology integrates both CMOS and Bipolar technology on the same silicon substrate. CMOS offers high and symmetrical noise margin, high input impedance and low power consumption but for the speed constraint 29. In contrast, the Bipolar offers high drive current, high switching speed, smaller propagation delay, but very large scale integration is limited by its high power consumption. BiCMOS has made it possible to combine meritorious features of CMOS and Bipolar technology in a single process at reasonable cost to achieve the high density integration of CMOS with high current driving capability of bipolar transistors.


III. Scaling – Impact & Limitations

     Scaling of the transistors is the driving force for the IC technology which extends Moore’s law providing performance enhancement and increased device density.


A. Scaling of Planar MOSFET

The number of transistors per chip and the device performance has been improving exponentially over the last three decades. As the channel length is reduced, the performance improves, the power per switching event decreases, improves the drive current and device density 30. Scaling is driven by decreasing the channel length along with decrease in gate oxide thickness to increase the current drive of the transistor. However, increased electric field is encountered by this scaling. The demand for high performance and integration of transistors has accelerated the scaling trends in almost every critical parameter, such as lithography, effective channel length, gate dielectric thickness, supply voltage, device leakage, etc. Some of these parameters are approaching fundamental limits enabling alternatives to the existing material and exploration of new device structures in order to continue scaling 30.


B. Showstoppers of Planar CMOS Scaling

Recent unfavorable effects introduced by the scaling have become very prominent. First, the power density increases. Secondly, increase in interconnect delay, current density, and noise. Device parasitic resistance impacts the circuit performance by reducing the current drive and thus increases delay 22. Lastly, since the number of devices on a chip increases, the design and the testing becomes more difficult and time consuming. Main show stoppers for CMOS scaling are:


·       Increase on off-state current and parasitic currents like gate tunneling current, Direct Source-Drain tunneling which increases the static power of the devices.

·       Increase in parasitic capacitance, which increases the dynamic power of the devices.

·       Short Channel Effects (SCE) results in Drain Induced Barrier Lowering (DIBL), Hot carrier effects, Direct Source drain tunneling etc.

·       Drain Induced Barrier Lowering (DIBL)- Depletion region of source and drain can extend into the channel even without bias, as the channel length decreases. This phenomenon of the source and drain effectively taking part in channel charge, which would otherwise be controlled by the gate is known as charge sharing. Increase in drain bias increases the drain depletion region, and interacts with the source to channel junction and hence lowers the potential barrier. This is known as Drain Induced Barrier Lowering (DIBL). As a result of this reduced source junction barrier enables electrons get easily injected into the channel and the gate voltage loses its control over the drain current 28.

·       Hot carrier effect- The field in the reversed bias drain junction can lead to impact ionization and carrier multiplication. This result in holes contributes to substrate current and some may move to the source, where they lower source barrier and result in electron injected from source into p-region. Secondly, hot carrier effect causes the electrons to tunnel through the barrier into silicon oxide layer, where they get trapped in the oxide, thereby changing the threshold voltage and I-V characteristics of the device 28. 

·       Gate tunneling current- As the MOSFET is scaled, the gate oxide thickness is also reduced as per scaling rule. The ultra-thin gate oxide appreciates direct carrier tunneling from gate to channel.

·       Direct Source-Drain tunneling causes significant amount of carriers tunnel directly from source to drain through the barrier potential 3.

·       Lithography Challenges-Photolithography is an issue with continuous scaling. These are the results of incompetency of lithography-based techniques to provide the resolution below the wavelength of the light to manufacture CMOS devices 6. Extreme Ultra-violet (EUV) lithography has not yet arrived in industry yet 9.

·       Interconnect Delays-As the MOSFETs become smaller and faster, the interconnection delays on integrated circuit become increasingly important. Both the resistance of the metal lines and the capacitance between them go up resulting in unacceptable RC delays. The signal integrity is becoming one of the major design issues due to the increased coupling capacitance between interconnects.